Vex----problems with the Alu

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Vex----problems with the Alu

Postby Guest » Wed Jan 19, 2005 3:03 pm


despite the fact that in the manual is stated that it is possible to have 2 Alus in a cluster, when a number of alus smaller than 4 is inserted in the architecture the compilers delivers an error message (early beat Issue width Alu 0. .....)
no matter what value is inserted as Issue width.

If anyone may clarify this point that would be very useful for understanding appropriately the compiler's work.



Postby frb » Thu Jan 20, 2005 12:25 pm

Indeed, because some of the ASM operations require up to 4 ALUs, the compiler has some checks that prevent certain configurations of the machine model to be accepted.

In order to model a machine that is narrower than 4 ALUs, the best is to use the "IssueWidth" parameters, which constrains any operation (hence, ALUs as well) to the given limit.

For example, if you want to model a machine that can issue a maximum of 2 operations per instruction, you can use a machine model file that contains

RES: IssueWidth 2

Hope this helps,

-- Paolo
Posts: 62
Joined: Thu Nov 12, 2009 3:44 pm

Postby frb » Thu Jan 20, 2005 12:32 pm

In addition, remember that if you want to go in the other direction (ie, increase the number of ALUs > 4), you also have to remember to increase the IssueWidth. So, for example, to model a machine with 8 ALUs in cluster 0 and an issue width of 8, you have to pass these 2 parameters

RES: IssueWidth 8
RES: Alu.0 8

If you omit the first parameter, you are modeling a machine with 8 ALUs, but that can only issue 4 (the default) operations per instructions, which might not entirely make a lot of sense....

-- Paolo
Posts: 62
Joined: Thu Nov 12, 2009 3:44 pm

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