problem related to IssueWidth

Usage of VEX tools

problem related to IssueWidth

Postby giovansaloni » Fri Jan 21, 2005 5:52 pm

Hi all,
I have some doubts regarding Vex configuration parameters:

- If I understood correctly Issuewidth is system related, not cluster related. So, let's suppose we have a two clustered architecture, with one ALU in each cluster (not so a meaningful configuration, anyway...). I can't declare less than four ALUs for each cluster, so I have to use the IssueWidth parameter; but, if a declare an IssueWidth = 2 the compiler schedules two instruction per cycle, regardless of the cluster.
Does someone know a way out? (so that I can use always one unit per cluster per cycle?)

- In the VeryWide Architecture described on the last page of the VEX System manual, IssueWidth equals 32, while we have four 32-ALUs, 32-MPYs clusters. Shouldn't IssueWidth be 32*4= 128 in order to access all the units?

- Do I have to place an ALU for every instruction (RISC-like) or I can have some position filled only by MPYs? Or do I have to place a ALU beside every MPYs on the same bus section? In other words, must the number of ALUs be equal to the Issuewidth or must the number of ALUs plus the number of Multipliers be equal or greater then the Issuewidth?



Thanks for help
Giovanni Ansaloni
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Re: problem related to IssueWidth

Postby frb » Fri Jan 21, 2005 7:40 pm

Here are some answers to your questions.

giovansaloni wrote:If I understood correctly Issuewidth is system related, not cluster related. So, let's suppose we have a two clustered architecture, with one ALU in each cluster (not so a meaningful configuration, anyway...). I can't declare less than four ALUs for each cluster, so I have to use the IssueWidth parameter; but, if a declare an IssueWidth = 2 the compiler schedules two instruction per cycle, regardless of the cluster.
Does someone know a way out? (so that I can use always one unit per cluster per cycle?)

There is currently no good way to model what you are trying to model. You can say "IssueWidth=k" and model an architecture that issues k ops per instruction. However, if you go to a clustered model, you are right that the compiler is free to issue any combination of those ops. In other words, you currently cannot model a 2-cluster architecture with 1-issue per cluster. You can only model a 2-cluster architecture with 2-issue regardless of the cluster. What is missing is an "IssueWidth.0" and "IssueWitdh.1", etc. parameter (issue width per cluster). I'll consider adding it to a successive version, but for the time being that is outside of what the current resource combinations support.

giovansaloni wrote:In the VeryWide Architecture described on the last page of the VEX System manual, IssueWidth equals 32, while we have four 32-ALUs, 32-MPYs clusters. Shouldn't IssueWidth be 32*4= 128 in order to access all the units?

The "verywide architecture" is a simple example. Yes, if you want to have up to 128 ops/instr you have to say IssueWidth=128. The example in the manual was for an architecture that can issue up to a max of 32 ops/instr (and of these, you can have 32 ALUs per cluster). This architecture is not something that someone would actually build (it wouldn't be too smart), just an illustrative example.


giovansaloni wrote:Do I have to place an ALU for every instruction (RISC-like) or I can have some position filled only by MPYs? Or do I have to place a ALU beside every MPYs on the same bus section? In other words, must the number of ALUs be equal to the Issuewidth or must the number of ALUs plus the number of Multipliers be equal or greater then the Issuewidth?


The resources are not correlated. You can build architecture with any combination. However, meaningful architectures (for a 1-cluster configuration) are the ones where IssueWidth >= ALUs. Most of your operations are going to be ALUs. When it comes to choosing MPYs (or memory, etc.) you can probably imagine cases where any other combination makes some sense.

Hope this helps,

-- Paolo
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Postby frb » Tue Aug 01, 2006 10:51 pm

NOTE: THIS IS FIXED IN VERSION 3.38 (and later)
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